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M62352AGP
8-bit 12ch D/A Converter with Buffer Amplifiers
REJ03D0867-0300 Rev.3.00 Mar 25, 2008
Description
M62352A is a CMOS structured semiconductor integrated circuit integrating 12 channels of built-in D/A converters with high performance buffer operational amplifier or each channel output. The 3-wire serial interface (DI, CLK, LD) method is used for the transfer format or digital data to allow connection with microcomputer with minimum wiring. DO terminal is provided to allow cascading serial use. Built-in buffer operational amplifiers are designed to operate or full swing in the whole voltage range from VCC to GND for each input/output. And their higher stability for capacitive load perfectly fits in to the use for electronic volume (VCA) or the replacement for semi-variable resistor for tuning.
Features
* * * * * 12-bit serial data input (3 wire serial data transfer method, DI, CLK, LD) Corresponds to TTL input for digital input (VINH 2 V, VINL 0.8 V) R-2R + segment method high performance 12ch 8-bit D/A converters 12ch buffer operational amplifiers operating in the whole voltage range from VCC to GND Buffer operational amplifiers with high oscillation stability for capacitive load
Application
Adjustment or control of industrial or home-use electronic equipments such as VTR camera, VTR set, TV, and CRT display.
Block Diagram
GND 20 AO2 19 AO1 18 DI 17 CLK 16 LD 15 DO 14 AO12 13 AO11 12 VCC 11
12-bit shift register
D0 1 2 3 4 5 6 D7 D8 9 10 D11
Ch2
8-bit R-2R + segment D/A converter
8-bit latch
.... (12) (12)
8-bit latch Ch3
8-bit R-2R + segment D/A converter
+ -
1 4
D/A
+ -
+ -
12 11
+ -
D/A Address decoder
........
D/A
D/A
L
(8)
L
L
(12)
L
5
L
6
L
7
L
8
L
9
L
10
L
D/A
D/A
D/A
D/A
D/A
D/A
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
1 VSS (VrefL)
2 AO3
3 AO4
4 AO5
5 AO6
6 AO7
7 AO8
8 AO9
9 AO10
10 VDD (VrefU)
REJ03D0867-0300 Rev.3.00 Mar 25, 2008 Page 1 of 8
M62352AGP
Pin Arrangement
M62352AGP
VSS (VrefL) AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 VDD (VrefU)
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
GND AO2 AO1 DI CLK LD DO AO12 AO11 VCC
(Top view) Outline: 20P2E-A
Pin Description
Pin No. 17 14 16 15 18 19 2 3 4 5 6 7 8 9 12 13 11 20 10 1 Pin Name DI DO CLK LD AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 VCC GND VDD VSS Function Serial data input terminal. 12-bit serial data is input to this terminal. Serial data output terminal. Serial data of 12-bit shift register is output from this terminal. Serial clock input terminal. Input signal from DI terminal is input to 12-bit shift register upon the rise of shift clock. Data is loaded to register when "H" is input to LD terminal. 8-bit D/A converter output terminal. Built-in buffer amp. is connected to VCC. D/A converted voltage between VDD and VSS is output to each terminal.
Power supply terminal. Digital and analog common GND D/A converter high level reference voltage input terminal. D/A converter low level reference voltage input terminal.
REJ03D0867-0300 Rev.3.00 Mar 25, 2008 Page 2 of 8
M62352AGP
Block Diagram for Explanation of Terminals
VCC
11
GND
20
DI CLK
17 16
D0 D1 D2 D3
12-bit shift register
D4 D5 D6 D7 D8 D9 D10 D11
14
DO
(8) (12)
Decoder
1 2 3 4 5 6 7 8 9 10 11 12
15
LD
..... 8-bit latch 8-bit D/A converter
..... 8-bit latch 8-bit D/A converter
..... 8-bit latch 8-bit D/A converter
..... ........... 8-bit latch ........... 8-bit D/A converter
..... 8-bit latch 8-bit D/A converter
..... 8-bit latch 8-bit D/A converter
+ -
A1 18
+ -
A4 19
+ -
........... A5 2
+ -
A10 9 .............
+ -
A11 12
+ -
A12 13 1
10
AO1 VDD (VrefU)
AO2
AO3
AO10
AO11
AO12
VSS (VrefL)
Absolute Maximum Rating
Item Supply voltage D/A converter High level reference voltage Digital input voltage Output voltage Power dissipation Operating temperature Storage temperature Symbol VCC VDD VIN Vout Pd Topr Tstg Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 150 -20 to +85 -40 to +125 Unit V V V V mW C C
REJ03D0867-0300 Rev.3.00 Mar 25, 2008 Page 3 of 8
M62352AGP
Electrical Characteristics
Digital Part (VCC, VrefU = 5 V 10%, VCC VrefU, GND, VrefL = 0.0 V, Ta = -20 to +85C, unless otherwise specified.)
Item Supply voltage Supply current Input leak current Digital input Low voltage Digital input High voltage Digital output Low voltage Digital output High voltage Note: Symbol VCC ICC IILK VIL VIH VOL VOH Min 4.5 -- -10 -- 2.0 -- VCC - 0.4 Limits Typ 5.0 1.5 -- -- -- -- -- Max 5.5 3.5 10 0.8 -- 0.4 -- Unit V mA A V V V V Conditions CLK = 1 MHz operation VCC = 5 V, IAO = 0 A VIN = 0 to VCC
IOL = 2.5 mA IOH = -400 A
Changes from M62352GP: Digital input voltage corresponds to TTL spec.
Analog Part (VCC, VrefU = 5 V 10%, VCC VrefU, GND, VrefL = 0.0 V, Ta = -20 to +85C, unless otherwise specified.)
Item Reference voltage pin current D/A converter High level reference voltage range D/A converter Low level reference voltage range Buffer amplifier output drive range Buffer amplifier output dive range Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitive load Buffer amplifier output impedance Symbol IrefU VDD (VrefU) VSS (VrefL) VAO IAO SDL SL SZERO SFULL CO RO Min -- 3.5 GND Limits Typ 1.5 -- -- Max 3.5 VCC VCC - 3.5 Unit mA V Conditions VrefU = 5 V, VrefL = 0 V, IAO = 0 A Data condition: at maximum current The output does not necessarily be the Values within the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range (VAO). IAO = 100 A IAO = 500 A Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.2 V VrefU = 4.79 V VrefL = 0.95 V (15 mV/LSB) VCC = 5.5 V Without load (IAO = +0 A)
0.1 0.2 -1 -1.0 -1.5 -2.0 -2.0 -- --
-- -- -- -- -- -- -- -- 5
VCC - 0.1 VCC - 0.2 1 1.0 1.5 2.0 2.0 0.1 --
V mA LSB LSB LSB LSB F
REJ03D0867-0300 Rev.3.00 Mar 25, 2008 Page 4 of 8
M62352AGP AC Characteristics (VCC, VrefU = 5 V 10%, VCC VrefU, GND, VrefL = 0.0 V, Ta = -20 to +85C, unless otherwise specified.)
Item Clock "L" pulse width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" hold time Data output delay time D/A output setting time Symbol tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO tLDD 30 60 200 100 100 70 -- -- -- -- -- -- -- -- -- -- -- -- -- 350 300 ns ns ns ns ns ns s Min 200 200 -- Limits Typ -- -- -- Max -- -- 200 Unit ns ns ns Conditions
CL 100 pF CL 100 pF, VAO: 0.5 4.5 V The time until the output becomes the final value of 1/2 LSB
Measurement Circuit
Input
DUT
Output CL 100 pF
Timing Chart
tCR tCKH tCF tCHL
CLK
tCKL tLDC
DI
tDCH tCHD tCHL tLDH
LD
tLDD
AO1 to AO12 output
tDO tDO
DO output
REJ03D0867-0300 Rev.3.00 Mar 25, 2008 Page 5 of 8
M62352AGP
Digital Data Format
Last LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 First MSB D11
DAC data
DAC select data
DAC Data
D0 0 1 0 1 : 0 1 D1 0 0 1 1 : 1 1 D2 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D6 0 0 0 1 : 1 1 D7 0 0 0 0 : 1 1 D/A Output (VrefU - VrefL) / 256 x 1 + VrefL [V] (VrefU - VrefL) / 256 x 2 + VrefL [V] (VrefU - VrefL) / 256 x 3 + VrefL [V] (VrefU - VrefL) / 256 x 4 + VrefL [V] : (VrefU - VrefL) / 256 x 255 + VrefL [V] VrefU [V] (1 LSB) (2 LSB) (3 LSB) (4 LSB) (255 LSB) (256 LSB)
Note: VrefU = VDD, VrefL = VSS
DAC Select Data
D8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC Selection Don't care AO1 select AO2 select AO3 select AO4 select AO5 select AO6 select AO7 select AO8 select AO9 select AO10 select AO11 select AO12 select Don't care Don't care Don't care
Timing Chart (Model)
CLK
SI
D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LD AO1 to AO12
REJ03D0867-0300 Rev.3.00 Mar 25, 2008 Page 6 of 8
M62352AGP
Typical Application
11 VCC 10 VDD (VrefU) AO1 18 AO2 19 AO3 AO4 18 DI AO5 17 CLK MCU 16 LD 15 DO AO6 AO7 AO8 AO9 AO10 5 6 7 8 9 4 2 3
AO11 12 AO12 13 GND 20 VSS (VrefL) 1
Precaution for Use
M62352AGP has 3 terminals (VDD, VCC, and VSS) to which constant voltage is to be applied. Ripple voltage or spike noise to these terminals may worsen converting precision or cause erroneous operations. So be sure to use this device by putting capacitor between each terminal and GND to get D/A conversion operation stabilized. Output buffer amplifiers have high oscillation stability against capacitive load. This means that jitters by wirings around output terminals or capacitor between output and GND (0.1 F Max.) do not cause any problems with DAC operations. Connect capacitor (0.1 F or around) between output and GND for protection from spark discharge when this device is used under such high electric field as that for instance of instruments with cathode ray tube.
REJ03D0867-0300 Rev.3.00 Mar 25, 2008 Page 7 of 8
M62352AGP
Package Dimensions
20P2E-A
EIAJ Package Code SSOP20-P-225-0.65 JEDEC Code -- Weight(g) 0.08 Lead Material Alloy 42
Plastic 20pin 225mil SSOP
e b2
20
11
HE
E
F Recommended Mount Pad Symbol
1 10
e1
A
G
D
b
e
x
M
A2
A1
y
c z Z1 Detail G Detail F
A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2
Dimension in Millimeters Min Nom Max -- -- 1.45 0 0.1 0.2 -- -- 1.15 0.17 0.32 0.22 0.13 0.15 0.2 6.4 6.5 6.6 4.3 4.4 4.5 -- -- 0.65 6.2 6.4 6.6 0.3 0.5 0.7 -- -- 1.0 0.325 -- -- 0.475 -- -- 0.13 -- -- -- -- 0.1 -- 0 10 -- -- 0.35 -- -- 5.8 -- -- 1.0
L1
REJ03D0867-0300 Rev.3.00 Mar 25, 2008 Page 8 of 8
L
I2
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